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| AN231E04 Datasheet Rev 1.0 3rd Generation Dynamically Reconfigurable dpASP This device is RoHS compliant www.anadigm.com DS231000-U001d -1- Disclaimer Anadigm reserves the right to make any changes without further notice to any products herein. Anadigm makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Anadigm assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including with out limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Anadigm does not in this document convey any license under its patent rights nor the rights of others. Anadigm software and associated products cannot be used except strictly in accordance with an Anadigm software license. The terms of the appropriate Anadigm software license shall prevail over the above terms to the extent of any inconsistency. (c) Anadigm(R), Inc. 2007 All Rights Reserved. DS231000-U001d -2- AN231E04 Datasheet - Dynamically Reconfigurable dpASP PRODUCT AND ARCHITECTURE OVERVIEW The AN231E04 device is an "Analog Signal Processor"; ideally suited to signal conditioning, filtering, gain, rectification, summing, subtracting, multiplying, etc. The device also accommodates nonlinear functions such as sensor response linearization and arbitrary waveform synthesis. The AN231E04 device consists of a 2x2 matrix of fully Configurable Analog Blocks (CABs), surrounded by programmable interconnect resources and analog input/output cells with active elements. On chip clock generator block controls multiple non-overlapping clock domains generated from an external stable clock source. Internal band-gap reference generator is used to create temperature compensated reference voltage levels. The inclusion of an 8x256 bit look-up table enables waveform synthesis and several non-linear functions. Configuration data is stored in an on-chip SRAM configuration memory. An SPI like interface is provided for simple serial load of configuration data from a microprocessor or DSP. This memory is shadowed allowing a different circuit configuration to be loaded as a background task without disrupting the current circuit functionality. The AN231E04 device features seven configurable input/output structures each can be used as input or output, 4 of the 7 have integrated differential amplifiers. There is also a single chopper stabilized amplifier that can be used by 3 of the 7 output cells. Figure 1: Architectural overview of the AN231E04 device Circuit design is enabled using Anadigmdesigner2 software, a high level block diagram based circuitry entry tool. Circuit functions are represented as CAMs (Configurable Analog Modules) these are configurable block which map onto portions of CABs. The software and a development board facilite instant prototyping of any circuit captured in the tool. With dynamic reconfigurability, the functionality of the AN231E04 can be reconfigured in-system by the designer or on-the-fly by a microprocessor. A single AN231E04 can thus be programmed to implement multiple analog functions and/or to adapt on-the-fly to your circuit requirements. PRODUCT FEATURES * * * * * * * * * * * * * Dynamic reconfiguration Seven configurable I/O cells, two dedicated output cells Fully differential architecture I/O buffering with single ended to differential conversion Low input offset through chopper stabilized amplifiers 256 Byte Look-Up Table (LUT) for linearization and arbitrary signal generation Typical Signal Bandwidth: DC-2MHz (Bandwidth is CAM dependent) Signal to Noise Ratio: o Broadband 90dB o Narrowband (audio) 120dB Total Harmonic Distortion (THD): 100dB User controlled Compensated low DC offset <250V DC Offset via chopper stabilized architecture <50uV Package: 44-pin QFN (7x7x0.9mm) o Lead pitch 0.5mm Supply voltage: 3.3V APPLICATIONS * * * * * * * * * * * * Analog Signal Processing RFID IF (Baseband Filtering) Real-time software control of analog system peripherals Intelligent sensors Adaptive filtering and control Adaptive DSP front-end Adaptive industrial control and automation Self-calibrating systems Compensation for aging of system components Dynamic recalibration of remote systems Ultra-low frequency signal conditioning Custom analog signal processing ORDERING CODES AN231E04-e2-QFNTY AN231E04-e2-QFNTR dpASP Tray (260 /tray, 2600/box) dpASP Tape & Reel (1000 /reel, 4000/box) AN231E04-e2-QFNSP AN231K04-DVLP3 dpASP Sample Pack AN231E04 Development Kit [For more detailed information on the features of the AN231E04 device, please refer to the AN131E04/AN231E04 User Manual] DS231000-U001d -3- 1 1.1 AN231E04 Datasheet - Dynamically Reconfigurable dpASP ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings a Parameter DC Power Supplies Symbol AVDD BVDD DVDD Min -0.5 -0.5 Typ - Max 3.6 V 0.5 Unit V V Comment AVSS, BVSS and DVSS all held to 0.0 V Ideally all supplies should be at the same voltage (Theoretical values based on Tj=125deg.C) Still air, No heatsink, 44 pads and exposed die pad soldered to PCB ja = 22.5C/W. VDD = 3.3V Maximum power dissipation all resources used, (see section 1.5.13 for more detail). xVDD to yVDD Offset Package Power Dissipation, Pmax 25C Pmax 85C - - 4.5 1.8 W AN231E04 max power dissipation Input Voltage Ambient Operating Temperature Storage Temperature a dpASPmax Vinmax Top Tstg VSS-0.5 -40 -40 - 0.25 VDD+0.5 85 125 W V C C Absolute Maximum DC Power Supply Rating - The failure mode is non-catastrophic for VDD of up to 5 volts, but will cause reduced operating life time. The additional stress caused by higher local electric fields within the CMOS circuitry may induce metal migration, oxide leakage and other time/quality related issues. 1.2 Recommended Operating Conditions Symbol AVDD BVDD DVDD Min 3.0 Typ 3.3 Max 3.6 Unit V Comment AVSS, BVSS and DVSS all held to 0 V Conditional on the circuit which is being driven. This limit is defined as maximum signal amplitude through input Sample and hold cell which results in >-80dB THD+N using a 1KHz test signal. VMR is 1.5 volts above AVSS Assume a package ja=22.5C/W Parameter DC Power Supplies Analog Input Voltage. Vina VMR -1.375 - VMR +1.375 V Digital Input Voltage Junction Temp b b Vind Tj 0 -40 - DVDD 125 V C To calculate the junction temperature (Tj) you must first empirically determine the current draw (total Idd) for the design. The programmable nature of this device means this can vary by orders of magnitude between different circuit designs. Once the current consumption is established then the following formula can be used; Tj = Ta + Idd x VDD x 22.5 C/W, where Ta is the ambient temperature. Worst case ja = 22.5 C/W assumes no air flow and no additional heatsink, 44 pads and the exposed die pad soldered to PCB. 1.3 General Digital I/O Characteristics (VDD = 3.3v +/- 10%, -40 to 85 deg.C) Symbol Vih Vil Vol Voh Iil Cmax Rmin Fmax CLKduty Min 0 70 0 80 50 45 Typ 16 Max 30 100 20 100 +/-1 10 40 55 Unit A pF Kohm MHz % Each pins has a specific load driving capability, detailed in sections 1.4 and 1.5 Divide down to <4 MHz prior to use as a CAB clock All clocks Comment % of DVDD % of DVDD % of DVDD % of DVDD Some pins have active pull up/down, please see below. Parameter Input Voltage Low Input Voltage High Output Voltage Low Output Voltage High Input Leakage Current Max. Capacitive Load Min. Resistive Load ACLK Frequency Clock Duty Cycle DS231000-U001d -4- AN231E04 Datasheet - Dynamically Reconfigurable dpASP 1.4 Digital I/O Characteristics (VDD = 3.3v +/-10%, -40 to 85 deg.C unless commented) 1.4.1 Pins ACLK, SCLK, RESETb, CS1b, CS2b, SI, MODE (standard CMOS inputs) Symbol Vil Vih Min 0 70 Typ Max 30 100 Unit % % Comment % of DVDD % of DVDD Parameter Input Voltage Low Input Voltage High 1.4.2 Pin SO, (standard CMOS output) Symbol Vol Voh Cmax Rmin Min VSS 3.28 5 Typ Max VSS VDD 100 Unit mV V pF Kohm Comment Load 10pF//50Kohm to VSS Load 10pF//50Kohm to VSS VDD = 3.3 V. Maximum load 100 pF // 5 Kohm at up to 5MHz. Maximum load 100 pF // 5 Kohm at up to 5MHz. Pin shorted to VDD Current should be limited externally so that it does not exceed 3mA Pin shorted to VSS. Current should be limited externally so that it does not exceed 3mA Parameter Output Voltage Low Output Voltage High Max. Capacitive Load Min. Resistive Load Current Sink Isnkmax 60 100 135 mA Current Source Isrcmax 50 80 110 mA 1.4.3 Digital functions of mixed signal Pins IO1, IO2, IO3, IO4, IO5, IO6, IO7, These pins can be configured by the user to be standard CMOS input or outputs. I/O cells 5, 6 and 7 the pin pairs can be connected to and used individually. I/O cells 1 through 4 provide pin pairs for differential (complimentary) digital connections. Parameter Input Voltage Low Input Voltage High Output Voltage Low Output Voltage High Max. Capacitive Load Min. Resistive Load Symbol Vil Vih Vol Voh Cmax Rmin Min 0 70 VSS 3.25 50 Typ - Max 30 100 VSS VDD 50 - Unit % % mV V pF Kohm Current Sink Isnkmax 15 30 40 mA Current Source Isrcmax 15 25 35 mA Comment % of DVDD % of DVDD Pin load = 20pF//10K to VSS Pin load = 20pF//10K to VSS VDD = 3.3 V. Maximum load 20 pF // 10 Kohm at up to 4MHz signal Maximum load 20 pF // 10 Kohm at up to 4MHz signal Pin shorted to VDD. Current should be limited externally so that it does not exceed 3mA Pin shorted to VSS. Current should be limited externally so that it does not exceed 3mA. DS231000-U001d -5- AN231E04 Datasheet - Dynamically Reconfigurable dpASP 1.4 Digital I/O Characteristics continued (VDD = 3.3v +/-10%, -40 to 85 deg.C unless commented) 1.4.4 Pins ERRb (Open Drain, CMOS transistor) Symbol Vil Vih Vol Voh Cmax Rmin Min 0 70 VSS 3.29 50 Typ Max 30 100 7.0 VDD 10 Unit % % mV V pF Kohm Comment % of DVDD, % of DVDD 10KOhm to VDD VDD = 3.3 V. 10KOhm to VDD VDD = 3.3 V. Maximum load 10 pF // 50 Kohm at full BW Maximum load 10 pF // 50 Kohm at full BW Pin shorted to VDD. Current should be limited externally so that it does not exceed 3mA Pin shorted to VSS MUST be used Parameter Input Voltage Low Input Voltage High Output Voltage Low Output Voltage High Max. Capacitive Load Min. Resistive Load - Current Sink Current Source External Resistive Pullup Isnkmax Isrcmax Rpullupext 50 10 10 110 +/-1 10 mA A Kohm 1.4.5 Pins ACTIVATE, CFGFLGb These pins are Open Drain CMOS transistors, with optional user configurable internal pull-up resistor We also note that the output voltage on these pins is "sensed" by internal circuitry, (see figure 2 below) Parameter Input Voltage Low Input Voltage High Output Voltage Low Output Voltage High, internal pull-up. Output Voltage Low, external pull-up. Output Voltage High Max. Capacitive Load Min. Resistive Load Current Sink, pull down only Current Source, pull up only Internal Resistive Pullup External Resistive Pullup Symbol Vil Vih Vol Min 0 70 80 Typ Max 30 100 140 Unit % % mV - Voh VolE Voh Cmax Rmin Isnkmax Isrcmax Rpullupint Rpullupext 3.05 529 VDD 50 1.8 0.34 3.5 5 5.3 7.5 3.16 773 VDD 10 3.7 1.1 8.4 10 V mV V pF Kohm mA mA Kohm Kohm Comment % of DVDD % of DVDD Pin load = Internal pullup + external 10pF//50K to VSS VDD = 3.3 V. Pin load = Internal pullup + external 10pF//50K to VSS VDD = 3.3 V. Pin load = 5K to VSS VDD = 3.3 V. Pin load = 5K + 10pF to VSS Maximum load 10 pF // 50 Kohm at full BW Maximum load 10 pF // 50 Kohm at full BW Pin shorted to VDD. Pin shorted to VSS. Default, not used with external pullup. Optional - to be used only if internal pullup is deselected DS231000-U001d -6- AN231E04 Datasheet - Dynamically Reconfigurable dpASP 1.4 Digital I/O Characteristics continued (VDD = 3.3v +/-10%, -40 to 85 deg.C unless commented) 1.4.6 Pin LCCb/DOUT1 (CMOS Output) The primary function of this pin is as LCCb (Local Configuration Complete), this signal is used in multiple dpASP designs to pass Chips Select from dpASP to dpASP enabling primary configuration of a serial chain of dpASP's from a single SPI bus, please refer to the AN231E04 User Guide for details. If the LCCb signal pin is not required (e.g. a circuit design with a single dpASP device) then via dpASP configuration this pin can be used as a digital output, this is realized by adjusting the properties of the dpASP "digital I/O cell". Parameter Output Voltage Low, (LCCb) Output Voltage High, (LCCb) Symbol Vol(LCCb) Voh(LCCb) Min VSS 3.00 Typ - Max VSS 3.20 Unit mV V Output Voltage Low, (DOUT1) Vol(DOUT1) VSS - VSS mV Output Voltage High, (DOUT1) Max. Capacitive Load Min. Resistive Load Voh(DOUT1) Cmax Rmin 3.29 50 - VDD 10 - V pF Kohm Current Sink, (LCCb) Isnk(LCCb) 3.0 - 7.0 mA Current Source, (LCCb) Isrc(LCCb) 0.25 - 0.80 mA Current Sink, (DOUT1) Isnk(DOUT1) 20.0 - 60.0 mA Current Source, (DOUT1) Isrc(DOUT1) 12.5 - 35.0 mA Clock skew (DOUT1 connected to "clocka") CLKSKEW - 8.0 - ns Comparator skew (DOUT1 connected to "comparator") COMPSKEW - 25.0 - ns RAM transfer delay (DOUT1 connected to "RAM transfer Pulse") Auto-null/Osc start delay (DOUT1 connected to "Autonull/Osc start done" signal) 1 RAMDELAY - 20.0 - ns DONEDELAY - 40 - ms Comment Load 10pF//50Kohm to VSS, during configuration. Load 10pF//50Kohm to VSS, during configuration. VDD = 3.3 V Load 10pF//50Kohm to VSS, When configured to pin39=DOUT1 Load 10pF//50Kohm to VSS, When configured to pin39=DOUT1 VDD = 3.3 V. Maximum load 10 pF // 50 Kohm Maximum load 10 pF // 50 Kohm LCCb (pin 39) shorted to VDD, during configuration. Current should be limited externally so that it does not exceed 3mA. LCCb (pin 39) shorted to VSS, during configuration. DOUT1 (pin 39) shorted to VDD,. Current should be limited externally so that it does not exceed 3mA. DOUT1 (pin 39) shorted to VSS, Current should be limited externally so that it does not exceed 3mA. Skew at DOUT1 (pin 39) relative to external signal clock applied to input pin ACLK (pin 34). Note; This is only valid when DOUT1 is selected to output the CAM clockA, and CAM clockA is derived from ACLK divided by1. This is the delay of the comparator CAM output transition relative to the exported comparator clock clock appears on the output pin. Note, The comparator is clocked with a user programmable CAM clock derived from a division of ACLK This is the delay of the signal at the dpASP pin 39, (DOUT1) relative to the actual internal transfer event. This is the delay of the signal at the dpASP pin 39, (DOUT1) relative to the actual internal event. 1 see application note AN231002 "Auto-nulling within the AN231E04" DS231000-U001d -7- AN231E04 Datasheet - Dynamically Reconfigurable dpASP 1.4 1.4.7 Digital I/O Characteristics, continued (VDD = 3.3v +/-10%, -40 to 85 deg.C unless commented) MEMCLK/DOUT2 (CMOS Output) The primary function of this pin is as MEMCLK (Memory Clock), this signal is used as a clock output in circuit designs which require configuration from an SPI PROM (or SPI EEPROM), please refer to the AN231E04 User Guide for details. If the MEMCLK signal pin is not required (e.g. a circuit configured from a microcontroller) then via dpASP configuration this pin can be used as a digital output. The MEMCLK signal is only active when the dpASP MODE (pin35) is high (tied to VDD). DOUT2 function cannot be used if dpASP MODE (pin35) is high (tied to VDD). Parameter Output Voltage Low, (MODE pin 35 = VSS, DOUT2 inactive) Output Voltage Low, (MODE pin 35 = VSS, DOUT2 active) Output Voltage Low, (MODE pin 35 = VDD) Output Voltage High Max. Capacitive Load Min. Resistive Load Current Sink, (MODE pin 35 = VSS & DOUT2 inactive) Symbol Vol Min VSS Typ - Max VSS Unit mV Comment Load 10pF//50Kohm to VSS. This Pin MEMCLK is unused in this MODE=VSS, there is an internal weak pull down resistor Load 100pF//5Kohm to VSS Load 100pF//5Kohm to VSS Load 100pF//5Kohm to VSS, VDD = 3.3V. Maximum load 100 pF // 5 Kohm Maximum load 100 pF // 5 Kohm Pin shorted to VDD. Th This Pin MEMCLK is unused when MODE=VSS and DOUT2 is inactive. Thus No active drive. Pin shorted to VSS. This Pin MEMCLK is unused when MODE=VSS and DOUT2 is inactive. Thus No active drive. Pin shorted to VDD. Current should be limited externally so that it does not exceed 3mA Pin shorted to VSS. Current should be limited externally so that it does not exceed 3mA Skew at DOUT2 (pin 42) relative to external signal clock applied to input pin ACLK (pin 34). Note; This is only valid when DOUT2 is selected to output the CAM clockA, and CAM clockA is derived from ACLK divided by1. This is the delay of the comparator CAM output transition relative to the exported comparator clock clock appears on the output pin. Note, The comparator is clocked with a user programmable CAM clock derived from a division of ACLK This is the delay of the signal at the dpASP pin 42, (DOUT2) relative to the actual internal transfer event. This is the delay of the signal at the dpASP pin 42, (DOUT2) relative to the actual internal event. Vol Vol Voh Cmax Rmin Isnk VSS VSS 3.28 5 0.01 0.03 VSS VSS VDD 100 0.05 mV mV V pF Kohm mA Current Source, (MODE pin 35 = VSS & DOUT2 inactive) Current Sink, (MODE pin 35 = VDD or DOUT2 active) Current Source, (MODE pin 35 = VDD or DOUT2 active) Isrc - - +/-1 uA Isnk 60 100 135 mA Isrc 50 80 110 mA Clock skew (DOUT2 connected to "clocka") CLKSKEW - 8.0 - ns Comparator skew (DOUT2 connected to "comparitor") COMPSKEW - 25.0 - ns RAM transfer delay (DOUT2 connected to "RAM transfer Pulse") Auto-null/Osc start delay (DOUT2 connected to "Autonull/Osc start done" signal) 2 2 RAMDELAY - 20.0 - ns DONEDELAY - 40 - ms see application note AN231002 "Auto-nulling within the AN231E04" DS231000-U001d -8- AN231E04 Datasheet - Dynamically Reconfigurable dpASP 1.4.8 RAM Transfer - Trigger and Arm These digital inputs do not have dedicated pins, a connection exists within the dpASP, an external signal can be routed to either of these virtual pins from a type2 I/O cell (I/O cells 5, 6 and 7. Pins 15,16,17,18,19 or 20). The purpose of these virtual pins is to extend optional asynchronous timing control of the dpASP configuration to the user. Parameter Input Voltage Low Input Voltage High Minimum pulse width connected to where Pulse-Pulse edge delay Symbol Vil Vih TPW setup time TPT-T setup time Min 0 70 5 Typ Max 30 100 Unit % % ns Comment % of DVDD % of DVDD Time to register the event internally. Delay between pre-trigger and trigger. Need not be observed if pre-trigger is not used, is set at the end of configuration automatically. Delay from trigger rising edge to internal execute event. Duration of execute pulse guaranteed 1 ACLK period. Can be as long as 2 periods depending on relative phases. Pre-trigger circuit is reset ready to accept another pre-trigger. - - 10 - - ns Execute delay Execute minimum width TEXDLY 0 10 20 ns TMinEW Pre-trigger reset. 1 ALCK - 2 ACLK - TPTR 10 TPW - - ns TPTR Pre-trigger TPW TPT-T Trigger Internal RAM execute TEXDLY TMinEW edge (n) ACLK edge (n+1) AnadigmDesigner2 options, (these are set using the software tool AnadigmDesigner2) RAM Transfer Trigger = Automatic : RAM transfer happens automatically immediately after the "end" byte of a configuration bit stream. Timing control is entirely inside the AN231E04 device and not visible to a user. RAM Transfer Trigger = Event driven. RAM Trigger = Off. no pre-trigger used. The "end" byte of configuration bit stream arms the RAM transfer and the user signal then acts as the trigger. Arm Trigger = On External Signal Allowed = Trigger. This setting allows the external signal connected to be the trigger, Arming must be from an internal signal. External Signal Allowed = Arm. This setting allows the external signal connected to be the arming signal, Trigger be from an internal signal. RAM Transfer Trigger = Clock synch RAM transfer happens automatically immediately following the first occurrence of all internal clocks being scyncronous. Timing control is entirely inside the AN231E04 device and not visible to a user. HINT: The RAM transfer timings above are for the trigger block hardware - The Trigger and Arm signals can come from many sources, propagation delays to the trigger block inputs will vary depending on the source and routing of the signals to this block. DS231000-U001d -9- AN231E04 Datasheet - Dynamically Reconfigurable dpASP 1.5 1.5.1 Analog I/O Characteristics (VDD = 3.3v +/-10%, -40 to 85 deg.C unless commented) Analog Inputs General Symbol Vina Vdiffina Vcm VosIOInt VosIOAZ VosCabI VosCabAz VosCabzC Input Frequency Parameter Input Range Differential Input Common Mode Input Range Input Offset Min VMR 1.375 0 1.4 - Typ 1.5 3.0 0.5 3 250 75 Max VMR + 1.375 +/-2.75 1.6 18 1.0 18 1000 250 Unit V V V mV mV mV uV uV Comment VMR set to 1.5V VMR = 1.5 V. Limited by signal clipping for large waveforms. Please see figures IO cell, unity gain mode intrinsic IO cell, unity gain mode, auto-null on. CAB, unity gain mode. CAB, unity gain mode, auto-null on. CAB, unity gain mode, auto-null and chopping on. Max value is clock, CAM and input stage dependent. Input frequency for most CAMs is limited to approx <2MHz due to CAM signal processing which is based on sampled data architectures. Fain 0 <2 8 MHz 1.5.2 IO Differential Operational Amplifier Symbol Vinouta Vdiffioa Parameter Output voltage range Differential Input/Output Common Mode Input Voltage Range (Note1) Min VMR 1.375 - Typ - Max VMR+ 1.375 +/2.75 VMR Unit V V Comment VMR = 1.5V. Measured for IO SnH circuit. Common mode voltage = 1.5 V. Measured for IO SnH circuit. Limited due to causing signal clipping for large waveforms. VMR can be varied if supplied externally (+200mV to -1.0volt) Due to common mode offsets. Intrinsic offset voltage. Auto-null offset voltage, rectangular distribution. see application note AN231002 "Auto-nulling within the AN231E04" Auto-null mode, from -40C to 125C. Sample and Hold mode, 1MHz clk, at DC Sample and Hold mode, 1MHz clk, at DC Opamp driving off chip with Max load. Effective internal slew is affected by the internal routing and load is normally much faster 10pF external load Voltage gain mode Measured at package pins. Track impedance increases the Vcm VMR VMR V Common Mode Output Voltage Deviation from VMR Equivalent Input Voltage Offset. Equivalent Input Voltage Offset. Auto-null time, from LCCb falling edge. Offset Voltage Temperature Coefficient Power Supply Rejection Ratio Common Mode Rejection Ratio Vcm VoffsetI VoffsetAZ TAZ VoffsettAZ TC PSSR CMRR 60 60 23.5 3.0 500 60 4 - 72.7 18.0 1000 - mV mV uV ms V/C dB dB Differential Slew Rate Unity Gain Bandwidth. Open loop gain Input Impedance Output Impedance Slew UGB Av Rin Rout 10 - 50 63 103 33 - V/sec MHz dB Mohm Ohms DS231000-U001d - 10 - AN231E04 Datasheet - Dynamically Reconfigurable dpASP effective output impedance. The OpAmp is designed to drive all internal nodes, Output Load, External Output Load, External Noise Figure Signal-To Noise Ratio and Distortion Spurious Free Dynamic Range Rload Cload NF SINAD SFDR 1 0.16 97 96 100 Kohm pF V/Hz dB dB Unity gain mode. Unity gain mode. Unity gain mode. 1.5.3 IO Cell, Sample and Hold Mode Symbol Vina Vdiffina VosI VosAZ Parameter Input Range Equivalent Input Offset Voltage Min Typ Max Unit Comment Non auto-null differential opamp offset 3 Auto-null differential opamp offset3 With auto-null active. From -40C to 125C Generally limited by aliasing to half Sample and Hold clock. d.c. R=1/Cf equivalent Switched capacitances 0dBu input, 1KHz, Noise summed from 20Hz to 22KHz 0dBu input, 1KHz, Noise summed from 20Hz to 22KHz 0dBu input, 1KHz See analog input above 0 60 60 10 3 500 4 18 1000 2 8.0 mV uV V/C MHz dB dB Mohm pF V/Hz dB dB Offset Voltage Temperature Coefficient Input Frequency Power Supply Rejection Ratio Common Mode Rejection Ratio Input Resistance Input Capacitance Input Referred Noise Figure Signal-to Noise Ratio and Distortion Spurious Free Dynamic Range VoffsettcAZ Fain PSRR CMRR Rin Cin NF SINAD SFDR 0.16 84 90 1.5.4 Chopper Amplifier Cell Symbol Vina Vdiffina Ginamp GA 0dB GA10dB GA20dB GA30dB GA40dB VosI VosAZ1 VosAZ2 VoffsettcAZ Fain Parameter Input Range Gain Gain Accuracy Min 0dB - Typ 0.5 250 25 15 - Max 60dB 5 5 5 5 5 14 500 100 TBD - Unit % % % % % mV uV uV V/C KHz Comment Usable input range will be reduced by the effective gain setting 4 Software selected 0dB setting, 1KHz test signal. 10dB setting, 1KHz test signal. 20dB setting, 1KHz test signal. 30dB setting, 1KHz test signal. 40dB setting, 1KHz test signal. Intrinsic differential opamp offset Differential opamp offset, autonulled, NOT chopped. Differential opamp offset, autonulled and chopped. With auto-null and chopping active. From -40C to 125C Generally 10x slower than clock, application dependent. See analog input above Equivalent Input Offset Voltage Equivalent Input Offset Voltage Equivalent Input Offset Voltage Offset Voltage Temperature Coefficient Input Frequency 3 4 0 The sample and hold offset varies from phase1 to phase2. This is an average of both values To avoid clipping the maximum input range should be divided by the chopper gain DS231000-U001d - 11 - AN231E04 Datasheet - Dynamically Reconfigurable dpASP Power Supply Rejection Ratio Common Mode Rejection Ratio Large Signal Harmonic Distortion Input Resistance Input Capacitance Input Referred Noise Floor Input Referred Noise Floor Signal-to Noise and Distortion Ratio PSRR CMRR Dist Rin Cin IRN IRN 10 62 81 -77 5.0 dB dB dB Mohm pF nV/Hz nV/Hz DC. Amp Gain = 0dB 250kHz clock, 1kHz 0dBu output. See figure 1 Unity-gain. 0dBu input at 1KHz 20 4 SINAD - 76 - dB Spurious Free Dynamic Range SFDR - 90 - dB 20dB-gain, 250kHz clock. IIdle channel. 60dB-gain, 250kHz clock. IIdle channel. 20dB-gain, 250kHz clock. 0dBu output at 1KHz. Noise and distortion summed from 22Hz to 22KHz 20dB-gain, 250kHz clock. 0dBu output at 1KHz, See figure 2 Figure 1: ChopperAmplifier CMRR Figure 2: ChopperAmplifier SFDR 1.5.5 Analog Outputs, Loading & Signal Conditioning (The IO cells use the same circuits as the input cells) Parameter Min load R Rout Symbol RloadMin ROUTIO ROUTCAB Min 1 VMR1.375 - Typ 33 530 VMR - Max 100 VMR+ 1.375 - Unit KOhm Ohms Ohms pF V V mV Comment to VSS For IO opamp to package pins. For CAB opamp to package pins, (depends on CAB and IO used) Core to outside in bypass I/O. to VSS. Differential voltage where -80dB THD is reached for IO cell in SnH mode. 10pF load. Derived from on chip VMR voltage. Deviation from supplied VMR. Values are quoted for IO cell or CAB opamp. See other tables. Max load C Large signal swing Cload Max SIGLARGE Common Mode Voltage Common Mode Voltage Deviation Vcm VcmDV DS231000-U001d - 12 - AN231E04 Datasheet - Dynamically Reconfigurable dpASP 1.5.6 Clock Dividers Symbol DIVRATIOPR DIVRATIOSEC DIVAZ Parameter Division ratio Primary divider Division ratio secondary divider Division ratio auto zero clock Min clock speed Min 1 1 1000 Typ 162K 1kHz @ 25C) 10kHz @ 85C Max 510 510 510K Unit - Comment Software controlled. Software controlled. Typical is default value. Each CAM has a different lower clock frequency depending on the parameters set. Excessively low clock frequency will cause signal droop. Each CAM has a different upper clock frequency depending on the parameters set. Excessively high clock frequency will cause poor settling and loss of precision. Measured in terms of cycles of clock from a primary clock divider. CLKMIN - - KHz Max clock speed CLKMAX 8 MHz Phase delay PhaseD 0 - 255 cycles 1.5.7 PORb & Auto-null Symbol PorbDEL PorbBROWN Parameter Intrinsic Porb duration Porb brown out voltage Auto-null period 5 Min 0.5 0.8 - Typ 1 1.1 60 Max 2 1.5 - Unit ms V ms Comment After release of Porb pin. Porb will reset device if VDD drops below this level to prevent RAM corruption. Duration for AZ cycle of opamps AZDEL 1.5.8 VMR (voltage Mid Rail) and VREF (Reference Voltage) Ratings Symbol Vvmr Vref+ VrefVrefout Vrefout Vreftc PSSR PSSR Tstart Parameter VMR Output Voltage VREF+ Output Voltage VREF- Output Voltage Output Voltage Deviation VMR Output Voltage Deviation VREF+, VREFVoltage Temperature Coefficient VREF+, VMR, VREFPower Supply Rejection Ratio, VMR Power Supply Rejection Ratio Vref+ and VrefStart Up Time 5 Min 1491 2469 481 TBD TBD - Typ 1500 2492 501 0.5 1.0 - Max 1509 2515 520 1.0 2.0 1 Unit mV mV mV % % dB dB ms Comment At 25C, VDD=3.3 volts, see figure 3 At 25C, VDD=3.3 volts, see figure 4 At 25C, VDD=3.3 volts, see figure 4 Over process and supply voltage corners Over process and supply voltage corners See typical graphical data below -40C to 125C DC DC Assuming recommended capacitors, 25C, VDD=3.3 volts see application note AN231002 "Auto-nulling within the AN231E04" DS231000-U001d - 13 - AN231E04 Datasheet - Dynamically Reconfigurable dpASP VMR vs Temperature 1.498 1.497 1.496 1.495 1.494 1.493 1.492 1.491 1.49 1.489 -50 0 VMR [V] y = -7E-07x 2 + 9E-05x + 1.4946 R2 = 0.9992 50 T [C] 100 150 Figure 3: GainHold CMRR Differential VREF (VREF+ - VREF-) vs Temperature 1.986 1.985 1.984 1.983 1.982 1.981 1.98 1.979 1.978 1.977 -50 0 D_VREF [V] y = -9E-07x + 9E-05x + 1.9831 2 R = 0.9984 2 50 T [C] 100 150 Figure 4: GainHold CMRR DS231000-U001d - 14 - AN231E04 Datasheet - Dynamically Reconfigurable dpASP 1.5.9 CAB (Configurable Analog Block) Differential Operational Amplifier Symbol Vinouta Vdiffioa Common Mode Input Voltage Range 6 Common Mode Voltage Deviation Equivalent Input Voltage Offset. Equivalent Input Voltage Offset. Equivalent Input Voltage Offset. Offset Voltage Temperature Coefficient Offset Voltage Temperature Coefficient Power Supply Rejection Ratio Common Mode Rejection Ratio CMRR Differential Slew Rate, Internal SlewI 54 35 dB V/sec Vcm VcmD VoffsetI VosAZ VosAZchpI VosAZ VosAZChp PSSR Parameter Output Range Differential Output voltage Min 0.05 1.4 0 - Typ 1.5 3 250 75 see graph 60 Max 2.95 +/-2.9 1.6 +/-50 18 1000 250 19 < 0.1 - Unit V V V mV mV uV uV V/C V/C dB Comment GainInv 1kHz THD > -80dB. Common mode voltage = 1.5 V Limited by signal clipping. GainInv THD exceeds -80dB Common mode voltage = 1.5 V VMR set to 1.5V 6 Deviation is caused by opamp common mode offset voltages. Intrinsic offset voltage. Auto-null offset voltage. Auto-null & chopped offset Auto-null mode, from -40C to 125C. Auto-null and chopped mode, from -40C to 125C. DC. Variation between CAMs is expected because of variations in architecture. GainInv CAM, clock = 1MHz, gain = 1. -20dBu input at 1kHz See figure 6 Applicable when the OpAmp load is internal to the dpASP Applicable when the OpAmp driving signal out of the dpASP package. Routing resistance causes degradation from Slew Applicable when sourcing and loading the OpAmp with a load internal to the dpASP. CAMs limit signal frequency to a lower value. See figure 5 The OpAmp output is designed to drive all internal nodes, these are dominantly capacitive loads Output to a dpASP output pin (output cell bypass mode). This variable is influenced by CAB capacitor size, CAB clock frequency and CAB architecture Differential Slew Rate, External SlewE - 30 - V/sec Unity Gain Bandwidth, Full Power Mode. Input Impedance, Internal Output Impedance, Internal UGB - 18 - MHz Rin Rout 10 - - - Mohm Ohms Output Impedance, External Output Load, External 7 Output Load, External Input Referred Noise Floor 8 Signal-To Noise and Distortion Ratio 8 Spurious Free Dynamic Range 8 Rout - 600 - Ohms Rload Cload IRN 1 - 300 100 - Kohm pF nV/Hz Unity-gain GainHold CAM, 1MHz clocking. Idle channel. Unity-gain GainHold CAM, 1MHz clocking. 0dBu input at 1KHz, Noise and distortion summed from 22Hz to 22KHz Unity-gain GainHold CAM and SnH output cell. 1MHz clocking. 0dBu input at 1KHz. See figure 7 SINAD - 86 - dB SFDR - 100 - dB 6 7 The is for the OpAmp. The use of virtual earth architectures means the CAMs can exceed these values The maximum load for an analog output is 100 pF || 1 K Ohms. This load is with respect to AVSS. Using the DPASP with CAB Opamps driving directly off chip is not recommended. Full characterization of the performance of each application circuit by the designer is necessary 8 Using an I/O Cell Sample & Hold is used to prevent the variable routing resistance affecting the harmonic response DS231000-U001d - 15 - AN231E04 Datasheet - Dynamically Reconfigurable dpASP The idealized open loop gain plot is provided for information only. This information is associated with the dpASP in full power mode of operation. The dpASP operational amplifier open loop gain cannot be observed nor used when associated with external connections to the device. Internal reprogrammable routing impedances and switched capacitor circuit architectures using this operational amplifier limit the effective usable bandwidth. Figure 5: CAB Opamp Open Loop Gain Response Figure 6: GainHold CMRR Figure 7:GainHold SFDR DS231000-U001d - 16 - AN231E04 Datasheet - Dynamically Reconfigurable dpASP 1.5.10 CAB (Configurable Analog Block) Differential Comparator Parameter Input Range, External or Internal Differential Input, Internal Symbol Vina Vdiffina Min 0.0 - Typ - Max VDD - Unit V V Comment Will operate correctly. Set by internal signal clipping based on common mode voltage. 3.3VDD. In digital output mode, 10KOhms connected between output pins. Varies with internal routing. Pad buffers are recommended in this mode. In analogue Vref level output mode. 10KOhms connected between output pins. Will vary with internal routing. Zero hysteresis from -40C to 125C, Zero hysteresis Differential Output bypass (bypass with core comparator is not a recommended operating mode) VoutdiffL 0.163 - 3.138 V VoutdiffA Input Voltage Offset Offset Voltage Temperature Coefficient Setup Time, Internal Setup Time, External Delay Time Output Load Rload Output Load Cload Differential Hysteresis Differential Hysteresis Hysteresis Temperature Coefficient Hysta0 Hysta1 Hysttc1 Voffcomp Voffsettc Tsetint Tsetext Tdelay 0.592 1/2Td+25 10 0.78 1 - 2.396 1.22 125 500 11/2Td+25 mV V/C nsec nsec nsec Kohm - Voffcomp 10 10 50 - pF mV mV V/C Td = 1/Fc Fc = master clock frequency Applies if comparator drive off chip with output cell in bypass mode Applies if comparator drive off chip with output cell in bypass mode Hysteresis setting OFF Hysteresis setting ON Hysteresis setting = ON DS231000-U001d - 17 - AN231E04 Datasheet - Dynamically Reconfigurable dpASP 1.5.11 ESD Characteristics Pin Type Human Body Model 4000V 4000V 4000V 4000V 2000V 1500V 1500V Machine Model 250V 250V 250V 250V 200V 100V 100V Charged Device Model 4kV 4kV 4kV 4kV 4kV 4kV 4kV Digital Inputs Digital Outputs Digital Bidirectional Digital Open Drain Analog Inputs Analog Outputs Reference Voltages The AN231E04 is an ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate on the human body and test equipment and can discharge without detection. Although the AN231E04 device features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. 1.5.12 Power Consumption - Various Modes Parameter Deep sleep mode 1a Stand Standyby mode 1b Small circuit mode 1c Nominal circuit mode1d HighPower1e Symbol Idd Idd Idd Idd Idd Min - Typ 0.004 0.3 15 42 61 67 73 -2 Max 75 -10 Unit mA mA mA mA mA A/C Comment VDD=3.3 volts, Tj=25C VDD=3.3 volts, Tj=25C VDD=3.3 volts, Tj=25C VDD=3.3 volts, Tj=25C VDD=3.0 volts, Tj=85C VDD=3.3 volts, Tj=25C VDD=3.6 volts, Tj= -40C Temperature Coefficient for High power. 1a. 1b 1c. 1d - External clock stopped, all analog function disabled, memory active. External clock at 16MHz on ACLK, all analog functions disabled, memory active. dpASP active elements - Gain hold CAM, One IO in SnH and both clocked at 1MHz, One IO bypass, all references on. dpASP active elements - Four gain hold CAMs (4 CAB opamps), one CAB comparator, one CAB multiplier (1 CAB opamp, 1 CAB comparator, 1 CAB SAR ADC), Two IO in SnH, One IO in bypass, one simple IO in digital mode. 4 MHz clock for all, all references on. 1e dpASP active elements - Seven gain hold CAMs (seven CAB opamps), 1 arbitrary waveform generator (one CAB opamp, LUT, counter) 4 CAB comparators, 4 IO Sample and hold, references on, 4 MHz clock for all where possible, all references on. DS231000-U001d - 18 - AN231E04 Datasheet - Dynamically Reconfigurable dpASP PINOUT Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Pin Name I1P I1N O1N O1P AVSS O2P O2N I2N I2P AVDD I3P I3N O3N O3P IO5P IO5N IO6P IO6N IO7P IO7N O4P O4N I4N I4P BVDD VREFP VMR VREFN BVSS CFGFLGb CS2b CS1b SCLK ACLK MODE DVDD DVSS SI LCCb/ DOUT1 ERRb ACTIVATE MEMCLK/ DOUT2 SO RESETb Pin Type +ve Input -ve Input -ve Output +ve Output Ground Supply +ve Input -ve Input -ve Output +ve Output Positive Supply +ve Input -ve Input -ve Output +ve Output +ve Input/Output -ve Input/Output +ve Input/Output -ve Input/Output +ve Input/Output -ve Input/Output +ve Input -ve Input -ve Output +ve Output Positive Supply Reference load Reference load Reference load Ground Supply Digital Output Digital input Digital input Digital input Digital input Digital input Positive Supply Ground Supply Digital input Digital output Comments Type1 Input/Output cell. (IO Cell 1) Analog or digital input and output pins Analog ground, 0 Volts Type1 Input/Output cell. (IO cell 2) Analog or digital input and output pins Analog power 3.3 Volts Type1a Input/Output cell. (IO cell 3) Analog or digital input and output pins Type 2 Input/Output cell. (IO cell 5) Type 2 Input/Output cell. (IO cell 6) Type 2a Input/Output cell. (IO cell 7) Type1a Input/Output cell. (IO cell 3) Analog or digital input and output pins Voltage reference power 3.3 Volts Reference Voltage Noise suppression. Connected a 100nF capacitor from each pin to BVSS. The capacitive reservoir is used to sink and source peak current, thus reducing noise and maintaining stable reference voltages. Voltage reference ground 0 Volts Config status pin. Open Drain Output with optional internal Pull-up resistor. The output voltage is also sensed by internal circuitry, See figure XX for schematic. Chip select pin Device select CMOS, configuration logic strobe clock. CMOS, Analog clock input Connect to VSS (ACLK and SCLK sourced externally). Connect to VDD (ACLK sourced externally, MEMCLK & SO generated internally). Digital power 3.3 Volts Digital ground 0.0 Volts CMOS Serial data input. CMOS. Default function, Indicates Local Configuration Complete. Optional function (Single dpASP designs only), pin can be configured as user assignable signal path digital output under software control. Error indication. Open Drain, External Pull-up resistor must be used (10KOhms) See fig XXa Indicates Device activation. Open Drain Output with optional internal Pull-up resistor. The output voltage is also sensed by internal circuitry, See figure XX for schematic. Outputs MEMCLK clock when MODE pin = VSS. Caution - Do not load this pin during reset (NOT to be pulled low externally) Serial Out, ONLY used as an output for SPI-PROM setup bytes during configuration. Connected to VSS to reset the dpASP. If held low the dpASP will remain in reset (2msec delay internal set-up time follows release of RESETb (when this pin is pulled high)) 40 41 42 43 44 Digital output Digital Output Digital Output Digital Output Digital Input DS231000-U001d - 19 - AN231E04 Datasheet - Dynamically Reconfigurable dpASP MECHANICAL AND HANDLING The AN231E04 comes in the industry standard 44 lead QFN package. Dry pack handling is recommended. The package is qualified to MSL3 (JEDEC Standard, J-STD-020A, Level 3). Once the device is removed from dry pack, 30C at 60% humidity for not longer than 168 hours is the maximum recommended exposure prior to solder reflow. If out of dry pack for longer than this recommended period of time, then the recommended bake out procedure prior to solder reflow is 24 hours at 125C. The package is compliant with RoHS and is Lead-free. Lead finish is Matt tin (Sn-Cu). MEMCLK/DOUT2 LCCb/DOUT1 ACTIVATE RESETb MODE 35 DVSS DVDD ERRb 44 I1P I1N O1 O1 AVSS O2 O2 I2N I2P AVD I3P 1 2 3 4 5 6 7 8 9 10 11 12 43 42 41 40 39 38 37 36 34 33 32 31 30 ACLK SO SI SCLK CS1b CS2b CFGFLGb BVSS VREFN VMR VREFP BVDD I4P I4N AN231E04 29 28 27 26 25 24 23 22 13 14 15 16 17 18 19 20 21 O4P IO5N IO6N All dimension are in mm Symbol A A1 A2 A3 D D1 D2 b e f g Q1 R Min 0.00 5.30 0.20 0.26 0.2 Nom 0.01 0.65 0.20 7.00 6.75 5.50 0.25 0.50 0.42 Max 0.90 0.05 0.70 5.70 0.32 0.60 12' - 0.0' (Ang.deg. ) 0.09 - IO7N IO5P IO6P IO7P O3 O3P O4N I3N DS231000-U001d - 20 - AN231E04 Datasheet - Dynamically Reconfigurable dpASP QFN Package mechanical drawing TOP VIEW D1 Pin1 marker DIA 0,50 D 1.23 1 23 D 0.45 D1 A A2 D2 f f g Pin1 marker 0,20 R b D2 BOTTOM VIEW SIDE VIEW e g Q1 f g f DS231000-U001d - 21 - Seating Plane A1 A3 AN231E04 Datasheet - Dynamically Reconfigurable dpASP This page is empty DS231000-U001d - 22 - AN231E04 Datasheet - Dynamically Reconfigurable dpASP This page is empty DS231000-U001d - 23 - AN231E04 Datasheet - Dynamically Reconfigurable dpASP This page is empty http://www.anadigm.com For More information Contact support@anadigm.com DS231000-U001d - 24 - |
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